Conventional receivers for high speed serial communication systems may include a clock and data recovery circuit that extracts clock and data information from a received serial signal. For example, such a circuit may produce a clock signal synchronized with the incoming signal and the clock signal may then be used to recover data (e.g., data symbols) from the signal. Typically, the clock signal is generated at a frequency that matches the frequency of the data symbol rate in the received signal. The clock signal is then used to sample the received signal to recover individual data bits that correspond to each data symbol.
A clock and data recovery circuit may comprise a phase lock loop (“PLL”) or a delay lock loop (“DLL”) that aligns the edges, for example the rising edges, of a generated clock signal with the transition edges of the received signal (e.g., the edges of data symbols). As a result, the falling edges of the clock may be generated at times that coincide with approximately the middle of the data symbols. Thus, the falling edges of the clock signal may be used to sample the received signal in the middle of the data symbols.
In operation, however, bandwidth limitations inherent in the data communication media may tend to create increasing levels of data distortion as the data rate increases and as the channel length increases. For example, band-limited channels tend to spread transmitted pulses (e.g., as a result of micro-reflection in the channel). If the width of a spread pulse exceeds a symbol duration, overlap with neighboring pulses may occur. This condition is known as inter-symbol interference (“ISI”). In many applications, particularly high speed applications, relatively high levels of ISI may significantly degrade the performance of the receiver. Therefore, typical high speed receivers may include an adaptive equalizer (e.g., a decision feedback equalizer) that cancels or reduces ISI.
In some applications equalizer coefficients that control the adaptive equalization may be generated in accordance with data that is sampled from the received signal. For example, the received data may be equalized before it is sampled by, for example, a high speed retimer. To control the adaptive equalization, the equalized, but unsampled, data may be sampled by an analog to digital converter (“ADC”). The output of this analog to digital converter may then be used to generate coefficients for the adaptive equalizer using, for example, a least mean square adaptation algorithm.
In general, it may be desirable that the clock for the analog to digital converter be phase aligned with the clock for the retimer. Inaccuracy in the phase relationships may result in performance degradation of the receiver since the received signal may be equalized at a non-optimum point in time.